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g-link glt440l16 256k x 16 cmos dynamic ram with extended data output aug. 2000 (rev.1.1) g-link technology corporation 2701northwestern parkway santa clara, ca 95051, u.s.a. g-link technology corporation ,taiwan 6f, no. 24-2, industry e, rd, iv, science based industrial park, hsin chu, taiwan. - 1 - features : description : * 262,144 words by 16 bits organization. * fast access time and cycle time. * dual cas input. * low power dissipation. * read-modify-write, ras -only refresh, cas -before- ras refresh, hidden refresh and test mode capability. * 512 refresh cycles per 8ms. * available in 40-pin 400 mil soj and 40/44 pin tsop(ii) * single +3.3v 10% power supply. * all inputs and outputs are ttl compatible. * extended data- out(edo) page mode operation. the glt440l16 is a 262,144 x 16 bit high-performance cmos dynamic random access memory. the glt44016 offers fast page mode with extended data output, and has both byte write and word write access cycles via two cas pins. the glt440l16 has symmetric address and accepts 512-cycle refresh in 8ms interval. all inputs are ttl compatible. edo page mode operation allows random access up to 512 x 16 bits within a page, with cycle time as short as 14ns. the glt440l16 is best suited for graphics, and dsp applications requiring high performance memories. high performance 35 40 50 max. ras access time, ( t rac ) 35 ns 40 ns 50 ns max. column address access time, ( t ca a ) 13 ns 20 ns 25 ns min. extended data out page mode cycle time, ( t pc ) 14 ns 15 ns 19 ns min. read/write cycle time, ( t rc ) 45 ns 75 ns 90 ns max. cas access time, ( t cac ) 11 ns 12 ns 13 ns
g-link glt440l16 256k x 16 cmos dynamic ram with extended data output aug. 2000 (rev.1.1) g-link technology corporation 2701northwestern parkway santa clara, ca 95051, u.s.a. g-link technology corporation ,taiwan 6f, no. 24-2, industry e, rd, iv, science based industrial park, hsin chu, taiwan. - 2 - pin configuration : pin descriptions: name function a 0 - a 8 address inputs ras row address strobe ucas column address strobe/upper byte control lcas column address strobe/lower byte control we write enable oe output enable dq 1 - dq 16 data inputs / outputs v cc +3.3v power supply v ss 0v supply nc no connection glt440l16 soj top view tsop(type ii) top view
g-link glt440l16 256k x 16 cmos dynamic ram with extended data output aug. 2000 (rev.1.1) g-link technology corporation 2701northwestern parkway santa clara, ca 95051, u.s.a. g-link technology corporation ,taiwan 6f, no. 24-2, industry e, rd, iv, science based industrial park, hsin chu, taiwan. - 3 - absolute maximum ratings* capacitance* t a =25 c, v cc =3.3v 10%, v ss =0v operating temperature, t a (ambient) .....................................-10 c to +70 c storage temperature(plastic)....-55 c to +150 c voltage relative to v ss ............?.-1.0v to + 4.6v short circuit output current......................50ma power dissipation ......................................1.0w symbol c in1 c in2 c out parameter address input ras , lcas , ucas , we , oe data input/output typ 3 4 5 max. 4 5 7 unit pf pf pf * note :operation above absolute maximum ratings can abversely affect device reliability. *note: capacitance is sampled and not 100% tested electrical specifications l cas means ucas and lcas . l all voltages are referenced to gnd. l after power up, wait more than 100 m s and then, execute eight cas -before- ras or ras -only refresh cycles as dummy cycles to initialize internal circuit. block diagram : 512 oe clock generator we clock generator cas clock generator ras clock generator data i/o bus column decoders sense amplifiers i/o buffer memory array refresh counter . . x 0 - x 8 512 16 y 0 - y 8 9 i/o1 i/o2 i/o3 i/o4 i/o5 i/o6 i/o7 i/o8 oe we ras ucas v cc v ss a 0 a 1 a 7 a 8 address buffers and predecoders row decoders lcas i/o9 i/o10 i/o11 i/o12 i/o13 i/o14 i/o15 i/o16
g-link glt440l16 256k x 16 cmos dynamic ram with extended data output aug. 2000 (rev.1.1) g-link technology corporation 2701northwestern parkway santa clara, ca 95051, u.s.a. g-link technology corporation ,taiwan 6f, no. 24-2, industry e, rd, iv, science based industrial park, hsin chu, taiwan. - 4 - truth table: glt440l16 function ras casl cash we oe address dqs notes stanby h h h x x high-z read: word l l l h l row/col data out read: lower byte l l h h l row/col lower byte,data-out upper byte,high-z read: upper byte l h l h l row/col lower byte,high-z upper byte,data-out write: word(early write) l l l l x row/col data-in write: lower byte (early) l l h l x row/col lower byte,data-in upper byte,high-z write: upper byte (early) l h l l x row/col lower byte,high-z upper byte,data-in read write l l l h ? l l ? h row/col data- out,data-in 1,2 edo-page- mode read 1st cycle 2nd cycle l l h ? l h ? l h ? l h ? l h h l l row/col col data-out data-out 2 2 edo-page- mode write 1st cycle 2nd cycle l l h ? l h ? l h ? l h ? l l l x x row/col col data-in data-in 2 2 edo-page- mode read- write 1st cycle 2nd cycle l l h ? l h ? l h ? l h ? l h ? l h ? l l ? h l ? h row/col col data- out,data-in data- out,data-in 1,2 1,2 hidden refresh read write l ? h ? l l ? h ? l l l l l h h l l row/col row/col data-out data-in 2 2 ras -only refresh l h h x x row high-z cbr refresh h ? l l l x x high-z 3 notes: 1. these read cycles may also be byte read cycles (either ucas or lcas active). 2. these write cycles may also be byte read cycles (either ucas or lcas active). 3. early write only. 4. at least one of the two cas signals must be active ( ucas or lcas ).
g-link glt440l16 256k x 16 cmos dynamic ram with extended data output aug. 2000 (rev.1.1) g-link technology corporation 2701northwestern parkway santa clara, ca 95051, u.s.a. g-link technology corporation ,taiwan 6f, no. 24-2, industry e, rd, iv, science based industrial park, hsin chu, taiwan. - 5 - dc and operating characteristics (1-2) t a = 0 c to 70 c, v cc =3.3v 10%, v ss =0v, unless otherwise specified. sym. parameter test conditions access time min. typ max. unit notes i li input leakage current (any input pin) 0v v in 5.5v (all other pins not under test=0v) -10 +10 m a i lo output leakage current (for high-z state) 0v v out 5.5v output is disabled ( hiz) -10 +10 m a i cc1 operating current, random read/write t rc = t rc (min.) t rac = 35ns t rac = 40ns t rac = 50ns 160 145 125 ma 1,2 i cc2 standby current,(ttl) ras , ucas , lcas at v ih other inputs 3 v ss 4 ma i cc3 refresh current, ras -only ras cycling, ucas , lcas at v ih t rc = t rc (min.) t rac = 35ns t rac = 40ns t rac = 50ns 160 145 125 ma 2 i cc4 operating current, edo page mode ras at v il , ucas , lcas address cycling:t pc =t pc (min.) t rac = 35ns t rac = 40ns t rac = 50ns 160 145 125 ma 1,2 i cc5 refresh current, cas before ras ras , ucas , lcas address cycling: t rc =t rc (min.) t rac = 35ns t rac = 40ns t rac = 50ns 160 145 125 ma 1 i cc6 standby current, (cmos) ras 3 v cc -0.2v, ucas 3 v cc -0.2v, lcas 3 v cc -0.2v, all other inputs v ss 1 ma v cc supply voltage 3.0 3.6 v v il input low voltage -0.3 0.8 v 3 v ih input high voltage 2.0v v cc +0.3 v 3 v ol output low voltage i ol = 2ma 0.4 v v oh output high voltage i oh = -2ma 2.4 v notes: 1. i cc is dependent on output loading when the device output is selected. specified i cc (max.) is measured with the output open. 2.i cc is dependent upon the number of address transitions specified i cc (max.) is measured with a maximum of one transition per address cycle in random read/write and edo fast page mode. 3.specified v il (min.) is steady state operation. during transitions v il (min.) may undershoot to ?0.3v for a period not to exceed 20ns. all ac parameters are measured with v il (min.) 3 v ss and v ih (max.) v cc . ac characteristics
g-link glt440l16 256k x 16 cmos dynamic ram with extended data output aug. 2000 (rev.1.1) g-link technology corporation 2701northwestern parkway santa clara, ca 95051, u.s.a. g-link technology corporation ,taiwan 6f, no. 24-2, industry e, rd, iv, science based industrial park, hsin chu, taiwan. - 6 - t a = 0 c to 70 c , v cc = 3.3 v 10% v ih /v il = 2.0/0.8v , v oh /v ol = 2.0/0.8v an initial pause of 100 m s and 8 cas -before- ras or ras -only refresh cycles are required after power-up. 35 40 50 parameter symbol min. max. min. max. min. max. unit notes read or write cycle time t rc 70 75 90 ns read modify write cycle time t rwc 90 93 109 ns ras precharge time t rp 25 25 30 ns ras pulse width t ras 35 75k 40 100k 50 100k ns access time from ras t rac 35 40 50 ns 1,2,3 access time from cas t cac 11 12 13 ns 1,5,10 access time from column address t aa 18 20 25 ns 1,5,6 cas to output low-z t clz 0 0 0 ns cas to output high-z t cez 3 8 3 8 3 8 ns ras hold time t rsh 10 12 14 ns ras hold time referenced to oe t roh 7 8 9 ns cas hold time t csh 34 34 45 ns cas pulse width t cas 6 6 8 ns ras to cas delay time t rcd 13 24 18 28 19 37 ns ras to column address delay time t rad 10 17 13 20 14 25 ns 7 cas to ras precharge time t crp 5 5 5 ns row address set-up time t asr 0 0 0 ns row address hold time t rah 6 8 9 ns column address set-up time t asc 0 0 0 ns column address hold time t cah 5 6 7 ns column address to ras lead time t ral 18 20 25 ns column address hold time referenced to ras t ar 25 34 44 ns read command set-up time t rcs 0 0 0 ns read command hold time referenced to cas t rch 0 0 0 ns 4 read command hold time referenced to ras t rrh 0 0 0 ns 4 write command set-up time t wcs 0 0 0 ns 8,9 write command hold time t wch 5 6 7 ns write command pulse width t wp 5 6 7 ns write command to ras lead time t rwl 10 12 13 ns
g-link glt440l16 256k x 16 cmos dynamic ram with extended data output aug. 2000 (rev.1.1) g-link technology corporation 2701northwestern parkway santa clara, ca 95051, u.s.a. g-link technology corporation ,taiwan 6f, no. 24-2, industry e, rd, iv, science based industrial park, hsin chu, taiwan. - 7 - ac characteristics 35 40 50 parameter symbol min. max. min. max. min. max. unit notes write command to cas lead time t cwl 8 12 13 ns data set-up time t ds 0 0 0 ns data hold time t dh 5 8 9 ns data hold time referenced to ras t dhr 25 36 46 ns ras to we delay time t rwd 46 54 64 ns cas to we delay time t cwd 23 24 25 ns column address to we delay time t awd 29 32 37 ns ras to cas precharge time t rpc 0 0 0 ns access time from cas precharge t cpa 20 22 30 ns edo page mode cycle time t pc 14 15 20 ns edo page mode read-modify-write cycle time t prwc 45 50 59 ns cas precharge time (edo page mode) t cp 4 5 8 ns ras pulse width (edo page mode only) t rasp 35 100k 40 100k 50 100k ns access time from oe t oea 11 12 13 ns oe to data delay time t oed 5 8 8 ns oe to output high-z t oez 3 8 3 8 3 8 ns oe command hold time t oeh 5 7 7 ns data output hold after cas low t doh 3 3 5 ns ras to output high-z t rez 3 8 3 8 3 8 ns we to output high-z t wez 3 10 3 10 3 12 ns oe to cas hold time t och 8 8 8 ns cas hold time to oe t cho 8 8 8 ns oe precharge time t oep 8 8 8 ns cas set-up time for cas ?before- ras cycle t csr 8 10 10 ns cas hold time for cas ?before- ras cycle t chr 8 10 10 ns transition time t t 2 50 2 50 2 50 ns refresh period t ref 8 8 8 ms
g-link glt440l16 256k x 16 cmos dynamic ram with extended data output aug. 2000 (rev.1.1) g-link technology corporation 2701northwestern parkway santa clara, ca 95051, u.s.a. g-link technology corporation ,taiwan 6f, no. 24-2, industry e, rd, iv, science based industrial park, hsin chu, taiwan. - 8 - notes: 1. measure with a load equivalent to one ttl inputs and 50 pf. 2. assumes that t rcd t rcd (max.). if t rcd is greater than t rcd (max.), access time will be t aa dominant. 3. assumes that t rad t rad (max.). if t rad is greater than t rcd (max.), access time will be controlled by t cac . 4. either t rrh or t rch must be satisfied for a read cycle. 5. access time is determined by the longest of t caa , t cac and t cpa . 6. assumes that t rad 3 t rad (max.). 7. operation within the t rad (max.) limit ensures that t rac (max.) can be met. t rad (max.) is specified as a reference point only. if t rad is greater than the specified t rad (max.) limit, the access time is controlled by t caa and t cac . 8. t wcs , t rwd , t awd and t cwd are not restrictive operating parameters. 9. t wcs (min.) must be satisfied in an early write cycle. 10. t ds and t dh are referenced to the latter occurrence of cas of we . t t is measured between v ih (min.) and v il (max.). ac-measurements assume t t = 1.5 ns.
g-link glt440l16 256k x 16 cmos dynamic ram with extended data output aug. 2000 (rev.1.1) g-link technology corporation 2701northwestern parkway santa clara, ca 95051, u.s.a. g-link technology corporation ,taiwan 6f, no. 24-2, industry e, rd, iv, science based industrial park, hsin chu, taiwan. - 9 - read cycle row address column address data-out t rc t ras t rp t crp t csh t rcd t rsh t cas t crp t asr t rah t rad t asc t cah t ral t rch t rrh t ar t rcs t aa t oea t cez t oez t cac t clz t rac don't care v ih- v il- ras v ih- v il- cas v ih- v il- address v ih- v il- we v ih- v il- oe v oh- v ol- dq early write cycle note : d out = open t rp t rc t crp t csh t crp t rcd t rsh t cas t asr t rah t rad t asc t cah t ral t cwl t rwl t wcr t wch t wp t wcs t ar t ds t dh t dhr data - in column address row address v ih- v il- ras v ih- v il- cas v ih- v il- address v ih- v il- we v ih- v il- oe v ih- v il- dq don't care t ras
g-link glt440l16 256k x 16 cmos dynamic ram with extended data output aug. 2000 (rev.1.1) g-link technology corporation 2701northwestern parkway santa clara, ca 95051, u.s.a. g-link technology corporation ,taiwan 6f, no. 24-2, industry e, rd, iv, science based industrial park, hsin chu, taiwan. - 10 - late write cycle ( oe controlled write ) note : d out = open t rp t rc t crp t csh t crp t rcd t rsh t cas t asr t rah t rad t asc t cah t ral column address row address v ih- v il- ras v ih- v il- cas v ih- v il- address v ih- v il- we v ih- v il- oe v ih- v il- dq don't care t ras t rcs t cwl t rwl t wp t ds t oed t oeh t dh column address read - modify - write cycle t rp t rc t crp t crp t rcd t rsh valid data-out column address row addr. v ih- v il- ras v ih- v il- cas v ih- v il- address v ih- v il- we v ih- v il- oe v i/oh- v i/ol- dq don't care t ras valid data-in t cas t asr t rah t rad t asc t cah t csh t awd t cwd t rwl t cwl t wp t oea t clz t cac t aa t rac t dh t ds t oed t oez
g-link glt440l16 256k x 16 cmos dynamic ram with extended data output aug. 2000 (rev.1.1) g-link technology corporation 2701northwestern parkway santa clara, ca 95051, u.s.a. g-link technology corporation ,taiwan 6f, no. 24-2, industry e, rd, iv, science based industrial park, hsin chu, taiwan. - 11 - fast page read cycle t rasp t rp t crp t rcd t cas v ih- v il- ras v ih- v il- cas t cas t cas t cp t cp t pc t pc t rsh t asr t rad t rah t asc t cah t csh t asc t asc t cah t cah v ih- v il- address v ih- v il- we v ih- v il- oe dq v ih- v il- row addr. column address column address column address don't care t rcs t rch t rcs t rcs t rch t rrh t oea t cac t oea t cac t clz t rac t aa t oez t off t aa t clz t oez t oez t off t off t clz t aa valid data-uot valid data-uot valid data-uot fast page write cycle note : d out = open t rasp t rp t crp t rcd t cas v ih- v il- ras v ih- v il- cas t cas t cas t cp t cp t pc t pc t rsh t asr t rad t rah t asc t cah t csh t asc t asc t cah t cah t wcs t wp t wch t wcs t wcs t wch t wch t wp t wp t ds t ds t ds t dh t ds t ds v ih- v il- address v ih- v il- we v ih- v il- oe dq v ih- v il- row addr. column address column address column address valid data-in valid data-in valid data-in don't care t cwl t cwl t cwl t rwl t rhcp
g-link glt440l16 256k x 16 cmos dynamic ram with extended data output aug. 2000 (rev.1.1) g-link technology corporation 2701northwestern parkway santa clara, ca 95051, u.s.a. g-link technology corporation ,taiwan 6f, no. 24-2, industry e, rd, iv, science based industrial park, hsin chu, taiwan. - 12 - fast page mode late write cycle t rasp t rp t crp t rcd t cas v ih- v il- ras v ih- v il- cas t cas t cas t cp t cp t pc t rsh t asc t asc t cah t cah t ds t ds t dh t ds t dh v ih- v il- address v ih- v il- we v ih- v il- oe dq v ih- v il- row addr. column address column address column address valid data-in don't care t csh t rhcp t crp valid data-in valid data-in t asr t rah t rad t asc t cah t ral t rcs t wp t wp t wp t cwl t cwl t cwl t rcs t rcs t rwl t oeh t oeh t oeh t oed t oed t dh t oed hi-z hi-z hi-z fast page read - modify - write cycle t rasp t rp v ih- v il- ras v ih- v il- cas don't care t csh t rcd t cas t cp t cas t rsh t crp t rad t rah t asr t asc t cah t asc t cah t ral t prwc t rcs t wp t cwl t wp t cwl t rwl t cwd t awd t rwd t oea t cwd t awd t cpwd t oea t oeh t rac t aa t cac t oez t oed t ds t dh t aa t cac t oez t oed t ds t dh t clz t clz valid data-out valid data-in valid data-out valid data-in row addr. col. addr. col. addr. v ih- v il- address v ih- v il- we v ih- v il- oe v i/oh- v i/ol- dq
g-link glt440l16 256k x 16 cmos dynamic ram with extended data output aug. 2000 (rev.1.1) g-link technology corporation 2701northwestern parkway santa clara, ca 95051, u.s.a. g-link technology corporation ,taiwan 6f, no. 24-2, industry e, rd, iv, science based industrial park, hsin chu, taiwan. - 13 - cas before ras refresh cycle v ih- v il- ras t ras t ras t rp t rp t rc t rc t csr t csr t chr t chr t rpc t rpc t crp v ih- v il- cas ras -only refresh cycle v ih- v il- ras t ras t ras t rp t rp t rc t rc t rpc t crp v ih- v il- cas t crp t asr t asr t rah t rah row row address v ih- v il- hidden refresh cycle ( read ) t rp t crp t rcd v ih- v il- ras v ih- v il- cas t rac v ih- v il- address v ih- v il- we v ih- v il- oe dq v ih- v il- row address don't care t rp t cac t rcs t asc t cah t asr t cah t rad t ral t rsh t chr t rc t ras t ras column address t rc t whr t aa t oea t clz t off t oez data-out open
g-link glt440l16 256k x 16 cmos dynamic ram with extended data output aug. 2000 (rev.1.1) g-link technology corporation 2701northwestern parkway santa clara, ca 95051, u.s.a. g-link technology corporation ,taiwan 6f, no. 24-2, industry e, rd, iv, science based industrial park, hsin chu, taiwan. - 14 - hidden refresh cycle ( write ) note : d out =open t rp t crp t rcd v ih- v il- ras v ih- v il- cas t ds v ih- v il- address v ih- v il- we v ih- v il- oe dq v ih- v il- row address don't care t rp t dh t wp t wch t wcs t asc t cah t asc t cah t rad t rsh t chr t rc t ras t ras column address data-in t rc
g-link glt440l16 256k x 16 cmos dynamic ram with extended data output aug. 2000 (rev.1.1) g-link technology corporation 2701northwestern parkway santa clara, ca 95051, u.s.a. g-link technology corporation ,taiwan 6f, no. 24-2, industry e, rd, iv, science based industrial park, hsin chu, taiwan. - 15 - cas - before ras refresh counter test cycle t cas t cpt v ih- v il- ras v ih- v il- cas t rp t ras t csr t chr t rsh t ral t asc t aa t cac t rcs t rrh t rch t wrp t wrh t wrh t wrp t oea t cez t oez t clz t rwl t cwl t wch t wcs t wp t ds t dh t rcs t awd t cwd t rwl t cwl t wp t dh t ds t oed t oez t clz t cac t aa t oea open column address valid data-out valid data-in don't care valid data-in valid data-out v ih- v il- address v ih- v il- we v ih- v il- oe v oh- v ol- dq v ih- v il- we v ih- v il- oe v ih- v il- dq v ih- v il- we v ih- v il- oe v i/oh- v i/ol- dq read cycle write cycle read-modify-write t cah
g-link glt440l16 256k x 16 cmos dynamic ram with extended data output aug. 2000 (rev.1.1) g-link technology corporation 2701northwestern parkway santa clara, ca 95051, u.s.a. g-link technology corporation ,taiwan 6f, no. 24-2, industry e, rd, iv, science based industrial park, hsin chu, taiwan. - 16 - ordering information part number speed power feature package glt440l16-35j4 35ns normal edo 40l 400mil soj glt440l16-40j4 40ns normal edo 40l 400mil soj glt440l16-50j4 50ns normal edo 40l 400mil soj glt440l16-35tc 35ns normal edo 44l 400mil tsop glt440l16-40tc 40ns normal edo 44l 400mil tsop GLT440L16-50TC 50ns normal edo 44l 400mil tsop parts numbers (top mark) definition : glt 4 40 l 16 - 35 j4 note : c cdrom , h hdd. example : 1.glt710008- 15t 1mbit(128kx8)15ns 5v sram pdip(300mil)package type. 2.glt44016- 40j4 4mbit(256kx16)40ns 5v dram soj(400mil)package type. 4 : dram 6 : standard sram 7 : cache sram 8 : synchronous burst sram -sram 064 : 8k 256 : 256k 512 : 512k 100 : 1m -dram 10 : 1m(c/edo)* 11 : 1m(c/fpm)* 12 : 1m(h/edo)* 13 : 1m(h/fpm)* 20 : 2m(edo) 21 : 2m(fpm) 40 : 4m(edo) 41 : 4m(fpm) 80 : 8m(edo) 81 : 8m(fpm) *see note voltage blank : 5v l : 3.3v m : 2.5v n : 2.1v config. 04 : x04 08 : x08 16 : x16 32 : x32 speed -sram 12 : 12ns 15 : 15ns 20 : 20ns 70 : 70ns -dram 30 : 30ns 35 : 35ns 40 : 40ns 45 : 45ns 50 : 50ns 60 : 60ns package t : pdip(300mil) ts : tsop(type i) tc : tsop(type ll) pl : plcc fa : 300mil sop fb : 330mil sop fc : 445mil sop j3 : 300mil soj j4 : 400mil soj p : pdip(600mil) q : pqfp tq : tqfp
g-link glt440l16 256k x 16 cmos dynamic ram with extended data output aug. 2000 (rev.1.1) g-link technology corporation 2701northwestern parkway santa clara, ca 95051, u.s.a. g-link technology corporation ,taiwan 6f, no. 24-2, industry e, rd, iv, science based industrial park, hsin chu, taiwan. - 17 - package information 40/44 lead thin small outline package soj 40/44 lead thin small outline package tsop(type ii)

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